24:
118:
connected to the inverter output, its source connected to the power supply, and its drain connected to the inverter input. The keeper transistor thus connects the dynamic node to the power supply whenever it is supposed to be in the "1" state, allowing the output to be correctly restored despite the charge sharing.
76:
to speed up performance. In CMOS dynamic logic gates, the gate output is precharged to the power supply voltage while the clock is off (the "precharge" phase), and then is evaluated to the correct logic state while the clock is on (the "evaluation" phase) by draining the relevant NMOS transistors in
89:
In order to cascade dynamic logic gates, one solution is domino logic, which inserts an ordinary static inverter between stages. In a multistage domino logic cascade structure, the evaluation of each stage ripples the next stage for evaluation, similar to dominoes falling one after the other. Once
80:
When cascading dynamic logic gates, however, a problem arises: the precharge "1" state of the first gate may cause the second gate to discharge prematurely, before the first gate has reached its correct state. This uses up the precharge of the second gate, which cannot be restored until the next
117:
can cause difficulties for domino logic signal integrity; during the evaluation phase, NMOS transistors next to the output which are on may cause undesired discharging from the output node. To fix this, a keeper transistor can be used. This keeper transistor is a PMOS transistor with its gate
144:
Traditional domino logic circuits are "footed", that is, they have an NMOS transistor controlled by the clock which is connected to the ground rail. Some domino logic circuits, however, are "footless": they lack this transistor, resulting in higher speed at the cost of greater power leakage.
105:
to multiple pFETs; the dynamic gate connects to exactly one inverter, so the gate is still very fast. Furthermore, since the inverter connects to only nFETs in dynamic logic gates, it too is very fast. Second, the pFET in an inverter can be made smaller than in some types of logic gates.
137:). To rectify this property, some variants of domino logic are differential or dual-rail in nature, using inverted as well as non-inverted inputs to implement the logic function as well as its inverse. These varieties also include cross-coupled pFETs to attenuate
317:
57:
between domino stages to avoid premature discharge of further cascaded dynamic logic gates. Domino logic allows a rail-to-rail logic swing, with the output being able to switch from the power supply voltage to the ground voltage.
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Another issue in domino logic is its noninverting property; that is, it can only implement gates that do not have inversions at their outputs (such as
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67:
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315:, Abdel-Hafeez, S. & Ranjan, N., "Single Rail Domino Logic For Four-Phase Clocking Scheme", published 2000
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50:. Domino logic contrasts with other solutions to the cascade problem where cascading is interrupted by clocks or other means.
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46:. The term derives from the fact that in domino logic, each stage ripples the next stage for evaluation, similar to
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Domino logic was developed to speed up circuits, solving the premature cascade problem, typically by inserting
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While the insertion of the inverter might seem to defeat the point of dynamic logic, since the inverter has a
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General domino logic implementation, with the pull-down network symbolising a network of NMOS transistors.
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where possible, due to speed), there are two reasons it works well. First, there is no
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evaluated, the node states cannot return to "1" until the next precharge phase begins.
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333:"Low power domino logic circuits in deep-submicron technology using CMOS"
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Proceedings of the 8th Great Lakes
Symposium on VLSI (Cat. No.98TB100222)
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122:
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Natarajan, Suriyaprakash; Gupta, Sandeep K.; Breuer, Melvin A. (2001).
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techniques consisting of a dynamic logic gate cascaded into a static
261:
Proceedings
International Test Conference 2001 (Cat. No.01CH37260)
22:
512:
575:
423:
Wu, Chung-Yu; Cheng, Kuo-Hsing; Wan, Jinn-Shyan (January 1993).
35:
516:
425:"Analysis and design of a new race-free four-phase CMOS logic"
98:
94:
372:
Angeline, A. Anita; Bhaaskaran, V. S. Kanchana (2022-04-01).
179:
Sharma, Ankita; Rao, Divyanshu; Mohan, Ravi (December 2016).
188:
Journal of
Network Communications and Emerging Technologies
181:"Design and Implementation of Domino Logic Circuit in CMOS"
378:
Journal of the
Institution of Engineers (India): Series B
374:"Domino Logic Keeper Circuit Design Techniques: A Review"
72:
Dynamic logic differs from static logic by including a
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clock cycle, so there is no recovery from this error.
97:(one of the main goals of dynamic logic is to avoid
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597:
550:
456:Krambeck, R.H.; Lee, C.M.; Law, H.F. (June 1982).
331:Garg, Sandeep; Gupta, Tarun Kumar (2018-08-01).
212:"Issues in the design of domino logic circuits"
528:
8:
210:Srivastava, P.; Pua, A.; Welch, L. (1998).
535:
521:
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658:Current mode logic / Source-coupled logic
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16:For logic gates built from dominoes, see
264:. Vol. 13. IEEE. pp. 367–376.
458:"High-Speed Compact Circuits with CMOS"
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218:. IEEE Comput. Soc. pp. 108–112.
7:
462:IEEE Journal of Solid-State Circuits
429:IEEE Journal of Solid-State Circuits
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48:dominoes falling one after the other
155:Dynamic logic (digital electronics)
68:Dynamic logic (digital electronics)
337:Engineering Science and Technology
14:
496:Domino Logic, Boston University.
622:Direct-coupled transistor logic
1:
110:Modifications to domino logic
350:10.1016/j.jestch.2018.06.013
299:SC571 VLSI Design Principles
652:Transistor–transistor logic
508:Dynamic Logic, Paul DeMone.
295:"5. Dynamic Logic Circuits"
727:
640:Integrated injection logic
390:10.1007/s40031-021-00668-5
65:
15:
646:Resistor–transistor logic
634:Gunning transceiver logic
570:Depletion-load NMOS logic
482:10.1109/JSSC.1982.1051786
270:10.1109/test.2001.966628
224:10.1109/GLSV.1998.665208
77:the pull-down network.
610:Diode–transistor logic
85:Domino logic operation
28:
628:Emitter-coupled logic
582:Pass transistor logic
55:static CMOS inverters
26:
301:. Boston University.
38:-based evolution of
474:1982IJSSC..17..614K
441:1993IJSSC..28...18C
598:Other technologies
501:2016-03-04 at the
417:General references
29:
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576:Complementary MOS
233:978-0-8186-8409-8
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690:Four-phase logic
572:(including HMOS)
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74:clock signal
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32:Domino logic
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605:Diode logic
565:NMOS logic
560:PMOS logic
166:References
131:NAND gates
660:(CML/SCL)
406:256342548
398:2250-2114
359:2215-0986
135:NOR gates
123:AND gates
705:Category
590:(BiCMOS)
499:Archived
242:45670900
149:See also
127:OR gates
680:Dynamic
470:Bibcode
437:Bibcode
103:fan-out
675:Static
624:(DCTL)
578:(CMOS)
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668:Types
654:(TTL)
648:(RTL)
636:(GTL)
630:(ECL)
612:(DTL)
584:(PTL)
402:S2CID
238:S2CID
184:(PDF)
139:noise
99:pFETs
34:is a
642:(IL)
618:(OC)
394:ISSN
355:ISSN
274:ISBN
228:ISBN
133:and
125:and
95:pFET
36:CMOS
478:doi
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